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Usb Wiggler Jtag Pinout

author
Carole Stephens
• Sunday, 17 October, 2021
• 9 min read

The wiggler™ is a mid-cost interface used in the design, debug, and programming of microprocessor based embedded systems. One side of the wiggler interfaces to the USB port of a host IBM compatible PC and the other side connects to an OCD (On-Chip Debug) port of the target system.

jtag android downloads arm9 wiggler index
(Source: android.vslinux.net)

Contents

The interface connects to an on-chip test access port (TAP) that implements a stateful protocol to access a set of test registers that present chip logic levels and device capabilities of various parts. JTAG interface is supported by many devices as a convenient way of rewriting firmware (specially bootloaders) when other methods fail.

Using JTAG, the ROM memory can be directly written without soldering it from PCB to program it using a specific programmer. In most cases, you will need JTAG access to a device with a no longer working bootloader.

The device might get damaged or the interface will repeatedly throw communication errors. Buffered adapter is a better alternative, although it is a bit harder to build because it requires more parts.

Its main advantage is that the voltage levels match those expected by the device. The adapter uses only one integrated circuit (the 74HC244 line driver) and some common parts.

If you place a jumper on pins 1 and 2, power must be supplied by the target device through JTAG port (You can see if target device supplies power via JTAG port if D4 LED turns on). P1 pin header allows first to be pulled-up to supply voltage (using a jumper) if the CPU does not support open collector output.

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(Source: www.ebay.com)

The adapter can be built on a single sided 80 × 55 mm printed circuit board. Zenger diode D2 can be replaced with two series 1N4001 fitted in reverse order, to achieve a voltage drop of about 1.4 V that will raise output of voltage regulator to 4.7 V. If you use a 2.5 V regulator, you can raise its output to 3.3 V with a single 1N4001 fitted in reverse (2.5 + 0.7 = 3.2 V) or if you need 5 V level you can use 2.7 V Zenger diode.

Otherwise, you must power the adapter with a DC voltage of about 8 – 16 V via CON1 and place the jumper on pins 2 and 3 of header P2. It is open source and supports buffered cables (EA253, DLC5) but also buffered adapters like this one (Wiggler, Wiggler2).

The Wiggler is a low-cost interface used in the design, debug, and programming of microprocessor and microcontroller based embedded systems. One side of the Wiggler interfaces to the parallel port of a host IBM compatible PC and the other side connects to an OCD (On-Chip Debug) port of the target system.

One side of the wiggler interfaces to the USB port of a host IBM compatible PC. The other side connects to an OCD (On-Chip Debug) port of the target system.

It converts from the PC/ USB to the debug interface (10-pin DAY/SPD/SD, 20-pin Automotive JTAG) of an Infineon Microcontroller device. The software interface for tools is the WAS (Device Access Server) DLL.

jtag wiggler infodepot wikia pinouts universal thread board read
(Source: infodepot.wikia.com)

Clock rate up to 30 MHz (programmable) All signals are 5.5V, scaling down to 1.65V USB 2.0 (high-speed) Certified drivers for Microsoft Windows XP, VISTA, 7, and 8 USB, JTAG and DAY/SPD hot plug and unplug 3 on-board status LED Support for Automotive 20-pin JTAG on 10-pin DAY connectors Connector for frontend extensions (e.g. for galvanic isolation) added J-LINK is a USB powered JTAG emulator supporting many CPU cores.

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The Good FET is an open source tool for programming microcontrollers and memories by SPI, I2C, JTAG (MSP430, ARM), and a slew of vendor-proprietary protocols. Versa loon is a full-opensource multi-functional platform based on generic USB _TO_XXX protocol, which can now support more than 10 kinds of interfaces including ISP, JTAG, SD, SPI, IIC and so on.

Obioha in Java geschrieben, functionary BS our under Windows. Arm refers to a processor architecture, along with a large amount of intellectual property relating to microprocessor and microcontroller interfaces.

The “core” of the processors are distributed to manufacturers such as ST Microelectronics or NXP, and these manufacturers then add additional peripheral features, such as I2C and SPI interfaces, ADC's and Days, USB interfaces, and so on. Arm architectures are versioned as Arms, examples being ARMv2 (dating from 1987), ARMv6 (processors produced 2002-2005) and so on, and the processor cores which utilize those architectures are branded as Arms series (ARM1, ARM6, ARM7), and more recently as ARM Cortex-A/R/M series for high-performance (Cortex-A), real-time (Cortex-R), and microcontroller (Cortex-M) applications.

Arm’s debugging interface falls under the name of the Arm Foresight Architecture; this includes the debug interface (Arm Debug Interface, ADI), embedded trace macro cells (ETM), high-speed serial trace ports (HS STP), and Foresight program flow trace architecture. The APs can be Remaps, providing access to resources by addressing (analogous to memory mapping, hence the name), JTAG -APs, allowing JTAG scan chains to be connected to the whole debug unit (the DAY), and vendor-specific APs, which are not specified by Arm.

EXTENT (0b00000000) SAMPLE (0b00000001) PRELOAD (0b00000010) INTENT (0b00000100) CLAMP (0b00000101) HIGH (0b00000110) ABORT (0b11111000) DP ACC (0b11111010) APACE (0b11111011) INCOME (0b11111110) BYPASS (0b11111111) The general methodology here is that the debugger uses the JTAG or SD interface to execute instructions by going through the TAP state machine, then the instructions take the data and load it into the DP or an AP, and depending on the data, different registers within the DP or AP are accessed, providing the desired link to the system.

CTRL/STAT, used to control and obtain status information about the DPD LCR, Data Link Control register, controls the operating mode of the Data Link DLP IDR, Data Link Protocol Identification register, protocol version information DP IDR, Debug Port Identification register, Debug Port information EVENTS TAT, Event Status register, used by the system to signal an event to the external debugger REBUFF, Read Buffer register, provides a read operation; dependent on DP (JTAG or SD) SELECT, AP Select register, selects an Access Port and the active register banks with that AP; selects the DP address bank TARGETED, provides information about the target when the host is connected to a single device Instead of going further into the details, I would like to focus on the other type of debug port, the SWORD, and how it implements JTAG using only two wires.

While the JTAG -DP is a common and familiar example of a debugging interface, most relevant to our discussion is the JTAG alternative defined for Arm devices, the Arm Serial Wire Debug (SD). As microcontrollers tend to be quite dense in peripherals, most Cortex-M devices will implement SD in place of full JTAG to save pin real-estate.

To make this work, SD relies on the repetitive nature of JTAG operations: the state machine is manipulated, data is shifted in or out, and the process repeats. Instead, commands are issued serially over SDIO, and then that same pin is used for reading or writing data.

There are three phases to SD communication: packet request, acknowledgment, and data transfer. After a data transfer, the host is responsible for either starting a packet request, or driving the SD interface with idle cycles (clocking SDIO LOW).

A parity check is applied to packet requests and data transfer phases. Timing diagrams showing read and write operations for Serial Wire Debug.

If writing, the target provides a 3-bit ACK signal, then there is another turnaround period, followed by the 32-bit data to be written (DATA), and a parity bit. If an error has occurred, the ACK bits will indicate the fault, and the host can attempt to restart the operation.

The Arm IHI0031E document provides further timing diagrams to clarify various cases in communication, but the above are the primary use-cases. It is worth noting that there are (as of the time of writing) two versions of SD; SWDv1 supports only one connection between a host and a target (point-to-point), while SWDv2 implements single-host multiple-target communication (multi drop).

Throughout this series, we have learned where JTAG comes from, how it works, and how it’s used to debug and program devices. We’ve taken a look at the physical connections for JTAG, including the connectors and interfaces available, both commercial and open-source.

Finally, we concluded with an overview of the JTAG implementation for the popular Arm processor core technologies, including the SD two-wire interface. From here, we can go out and confidently use the debugging and programming features of our embedded devices, learning the particulars for different implementations, and making the best use of our time.

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